The Serial Peripheral Interface (SPI) bus is a synchronous serial communication interface protocol, whose specification is a use for short distance communication, typically between microcontrollers or processors and peripheral devices. FIG. 1A illustrates an SPI bus 10 between a single master device 12 and a single slave device 14. This is master-slave architecture with a single master as known in the art. The SPI bus defines four logic signals between the master 12 and slave 14 devices that include: SCLK (Serial Clock (output from master)), MOSI (Master Output, Slave Input (output from master)), MISO (Master Input, Slave Output (output from slave)), and SS (Slave Select (active low, output from master)). The master and slave devices 12, 14 may communicate and exchange data via the four logic signals.
The SPI bus protocol allows a single master device to communicate with multiple slave devices. As illustrated in FIG. 1B, master device 12, includes a dedicated slave select line to each slave device 14. The master device communicates with a particular slave device 14, by controlling the slave select SSn output line, to the slave device SSn input, typically by driving the desired slave select SSn line to a logic low signal level, while leaving the other slave SSn output select lines at a logic high signal level. The master device, while individually controlling the slave select lines of multiple slave devices 14, can communicate with a select slave of a plurality of slave devices 14, the master device 12 requires multiple output pins to accomplish this type of communication.
FIG. 1C illustrates known SPI bus communication between master device 12 and multiple slave devices 14 according to another communication setup. As shown, slave devices 14 are daisy-chained together. In this setup, master device 12 communicates with slave devices 14 using just the four logic signals on the SPI bus 10. As shown, the MOSI output of master device 12 connects to MOSI input of the first slave device 14, and the MISO output of the first slave device 14 connects to MOSI input of the next slave device 14 and so on. Using this connection architecture, the whole chain may act as a simple shift-register communication chain. If a transaction from the master device 12 to a single slave device 14 in the chain of slave devices takes N bits to complete, and if there are D number of devices in the SPI chain, the master device 12 needs to shift out N×D bits serially before closing the transaction. Furthermore, read data would have to be shifted out of the device chain (N×D bits), with the last slave device 14 in the chain sending its output data all the way back to the chain controller (i.e., master device 12) at the start of the chain.
The simple 4-wire interface of SPI becomes cumbersome when more and more slave devices connect to the serial chain. Suddenly, the master device 12 must drive 2 signals common to all devices in the chain: the sensitive clocking signal for the transaction and the slave select. If the chain were to grow too long, the master clock signal would need special consideration to supply clean, reliable edges to all slave clock input pins simultaneously. In addition, the device chain must be organized more like a circle to facilitate the MISO line from slave n back to the master. Since slave n's MISO line is the line that carries all read-back data to the master device in the chain, and in order to maintain timing, this line needs to be as short as possible. Therefore, the first and last slave devices in the chain would ideally be very near the master device controller.
Accordingly, a need exists for technology that overcomes the problem demonstrated above, as well as one that provides additional benefits. The examples provided herein of some prior or related systems and their associated limitations are intended to be illustrative and not exclusive. Other limitations of existing or prior systems will become apparent to those of skill in the art upon reading the following Detailed Description.